No próximo dia 16 de Julho às 15h, decorrerá mais uma palestra do DEEC na sala EA3. O convidado é o Prof. Pedro Trancoso, da Chalmers University of Technology e a sua palestra intitula-se:
NextGen Accelerators: Flexible, Scalable, Efficient - Together

Abstract: For a long time, computer systems have been built around an increasingly powerful general-purpose processor. Nevertheless, at some point these monolithic super chips were not able to deliver the expected additional performance due to limitations such as design complexity and power density. The decline of the monolithic processor gave way to new architectures. With efficiency as a main goal, domain-specific architectures, also known as accelerators, started playing an important role. The realization that one-size does not fit all resulted in an explosion of diverse accelerators for different applications and purposes, from both research and industry. Designers of these accelerators are usually faced with the tradeoff between a generic architecture that will stand the test of time and an application-dedicated architecture that is very efficient. We want both! As such, we focus on the design of building blocks for the next generation of accelerators. These blocks are efficient but at the same time can be combined in different ways to achieve the required flexibility and scalability. In this talk I will present some of our recent research results towards this goal.
Bio: Pedro Trancoso is a Full Professor at the Department of Computer Science and Engineering (CSE) of the Chalmers University of Technology, Sweden. He has an engineering degree from Instituto Superior Técnico (IST) (1993), Portugal and a MSc and PhD (1998) from the University of Illinois at Urbana-Champaign, U.S.A. His research interests are in computer architecture (memory hierarchy, multicore processors, reconfigurable computing, and energy efficiency) with main focus on the hardware acceleration for emerging applications such as machine learning. He is currently actively collaborating in several EU research projects (VEDLIoT, eProcessor and EPI SGA2) and SSF Swedish research projects (PRIDE, QuantumStack, AutoPIM), as well as the EUMaster4HPC EU Masters project on HPC. He is also the director of the Masters programme on High-Performance Computer systems (MPHPC) at Chalmers since its start in 2019.